A conventional output buffer circuit comprises a NOR circuit, a NAND circuit, a p-type metal-oxide-silicon field effect transistor (P-MOSFET), an n-type MOSFET (N-MOSFET), and first and second inverter circuits.
In operation, when a data signal changes from a high level to a low level, outputs of the NOR and NAND circuits become a high level. The first and second invertor circuits supply the P-MOSFET and the N-MOSFET with inverted signals of a low level, so that the P-MOSFET becomes ON state while the N-MOSFET becomes OFF state. As a result, the output data signal is charged up to become high.
On the other hand, when the data signal changes from a low level to a high level, the outputs of the NOR and NAND circuits become a low level. The first and second inverter circuits supply the P-MOSFET and the N-MOSFET with inverted signals of a high level, so that the P-MOSFET becomes OFF state, while the N-MOSFET becomes ON state. As a result, the output data signal is discharged to become low.
According to the conventional output buffer circuit, however, there is a disadvantage in that the power supply potential level changes to cause the wrong operation of other circuits which are formed with the output buffer circuit on a semiconductor substrate and supplied with a power from an external common power supply. Such a change of the power supply potential is caused by parasitic inductances existing between the external common power supply of the semiconductor substrate and a power supply of the output buffer circuit, when the data signal changes from a low level to a high level, and to a low level again before the output data signal is completely discharged to be the ground potential level, as well explained later.